IDT’08 Workshop > Friday, 19^th of December

IDT’08 Workshop > Saturday, 20^th of December

08:00-09:00

Registration

09:00-09:30

Conference Opening

09:30-10:30

Keynote 1 “Built-In-Self-Test and Digital Self Calibration of RFIC”

Chair: Mourad LOULOU – ENIS, Tunisia

Title: Built-In-Self-Test and Digital Self Calibration of RFICs

Keynote speaker: Mohammed Ismail El-NAGGAR

University:  The Analog VLSI Lab-The Ohio State University, USA

Abstract: To achieve the highest performance/price ratios of handheld wireless devices, the current trends in wireless chip set development call for multi-standard nanometer CMOS radios integrated on a single chip. This represents a grand challenge to the "yield" of such chip sets and typically requires several silicon spins which will increase the NRE development costs and may result in significant product delays and in missing important market windows. To meet this challenge, we present design techniques for built-in self-test (BIST) and digital self calibration of CMOS radio systems and demonstrate the validity of these techniques in the design of WiMAX/WLAN CMOS radio front ends.

10:30-11:00

Coffee break

11:00-13:00

Session A1: Networks-on-Chip

Chairs: Rached TOURKI – FSM, Tunisia
Omar HAMMAMI – ENSTA, France

• Norma: a Hierarchical Interconnection Architecture for Network on Chip
  Akram REZA, Midia RESHADI, Ahmad KHADEMZADEH, Maryam BAHMANI
  Islamic Azad University, Science and Research Branch – Iran / Iran Telecommunication Research Center – Iran

• Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA
  Bilel NEJI, Yassine AYDI, Rabie Ben-atitallah, Samy MEFTALI, Mohamed ABID, Jean-luc DEKEYSER
  CES, National Engineering School of Sfax (ENIS) – Tunisia / INRIA, University of Lille – France

• Design and Implementation of MIC@R Router for on Chip Networks
  Rafik BEN-TEKAYA, Adel BAGANNE, Kholdoun TORKI, Rached TOURKI
  Electronics and Micro-Electronics Lab, Faculty of Sciences at Monastir – Tunisia / LESTER Lab-CNRS, UBS University – France / CMP, INPG – France

• QSYN: Queueing Networks Synthesis for System on Chip
  Omar HAMMAMI
  ENSTA – France

• A Combined Packet and Circuit Switching Routing Algorithm for Networks-on-Chip
  Mohamed M. SABRY, Hassan SHEHATA BEDOR, M. Watheq EL-KHARASHI, Ashraf SALEM
  Ain Shams University – Egypt / Mentor Graphics – Egypt

• Networks-on-Chip Topology Generation Techniques: Area and Delay Evaluation
  Ahmed A. MORGAN, Haytham ELMILIGI, M. Watheq EL-KHARASHI, Fayez GEBALI
  Department of Electrical and Computer Engineering, University of Victoria – Canada / Mentor Graphics – Egypt

11:00-13:00

Session B1: Test Issues

Chairs: Bernard COURTOIS – CMP, France
Hassen MNIF – ISECS, Tunisia

• Increasing Testability in QCA Circuits Using a New Test Method
  A. ADINEH-VAND, G. LATIF-SHABGAHI, Mostafa RAHIMI AZGHADI
  Islamic Azad University – Iran / Power & Water University of Technology – Iran / Shahid Beheshti University – Iran

• QOS Testing of Service-Based Applications
  Maha DRISS, Yassine JAMOUSSI, Henda HAJJAMI BEN GHÉZALA
  National School of Computer Sciences (ENSI), RIADI-GDL Laboratory – Tunisia / IRISA-INRIA – France

• Universal Test Set For Bridging Fault Detection in Reversible Circuit
  Pradyut SARKAR, Susanta Chakrabarti
  Simplex Infrastructures Limited – India / Bengal Engg. & Science University – India

• Soundness Test Cases Generation for Duration Systems
  Lotfi MAJDOUB, Riadh ROBBANA
  LIP2 Laboratory, Tunisia Polytechnic School (EPT) – Tunisia

Chairs: Olivier DÉFORGES – INSA Rennes, France
Adel GHAZEL – SUP’COM, Tunisia

• Study of Different Pulse Waveforms and Analytical Probability of Error in TH-PAM Ultra Wideband Systems
  Moez HIZEM, Ridha BOUALLEGUE
  Research unity Systems of Telecommunication to Sup’ Com – Tunisia / National Engineers School of Sousse – Tunisia

• a SDR Interconnection Architecture Proposal for SATCOM Applications
  Mingda HUANG, Jojczyk LAURENT, Achille THOMAS, Carlos VALDERRAMA
  Faculty of Engineering – Belgium

• SRAM-FPGA Implementation of Masked S-Box Based DPA countermeasure for AES
  Najeh KAMOUN, Lilian BOSSUET, Adel GHAZEL
  CIRTA’COM Lab, SUP’COM – Tunisia / IMS Lab, ENSEIRB – France

• New Tunable Coplanar Microwave Phase Shifter with Nematic Crystal Liquid
  Fehim SAHBANI, Nicolas TENTILLIER, Ali GHARSALLAH, Christian LEGRAND
  LEMCEL – France / LPMM – France

• System Level Design of Radio Frequency Receiver for IEEE 802.16 Standard
  Dorra AYADI, Mourad LOULOU, Saul RODRIGUEZ, Mohammed ISMAIL
  LETI-ENIS – Tunisia / RaMSIS, KTH – Sweden /VLSI, Ohio – USA

• A Multi Objective Genetic Algorithm based Optimization of Wavelet Transform Implementation
  S. Fakhfakh GHRIBI, D. Sellami MASMOUDI and N. DERBEL
  ICOS-ENIS – Tunisia

• An analytical threshold voltage model for nanoscale GAA MOSFETs including effects of hot-carrier induced interface charges
  Z. GHOGGALI, F. DJEFFAL, M. A. ABDI, D. ARAR, N.LAKHDAR, T.BENDIB
  LEA, Department of Electronics, University of Batna – Algeria

• Why is CMOS scaling coming to an END?
  Nor Zaidi HARON, Said HAMDIOUI
  Computer Engineering Laboratory, Delft University of Technology – The Netherlands

• Design of buck converter circuits operating in weak-inversion region
  Youngkook AHN, Kitae KIM, Hyunseok NAM, Youngkil CHOI, Hyungdong ROH, Jeongjin ROH
  Department of Electrical Engineering, Hanyang University – Korea

• Wide Tuning Band Quadrature VCO
  Dorra MELLOULI, Hassene MNIF, Mourad LOULOU
  Research Unit on Electronics and Information Technologies, National Engineering School of Sfax (ENIS) – Tunisia

• Future Trends of Saw Filters
  Tarek HDIJI, Hassene MNIF, Mourad LOULOU
  LETI, National Engineering School of Sfax (ENIS) – Tunisia

• A voltage driver using the rail to rail operation in CMOS 0, 25 µm technology
  Fayçal MEDDOUR, Zohir DIBI, Souhil KOUDA, Mohamed Amir ABDI, Otto MANCK
  Laboratoire d’Electronique Avancée, Batna university – Algeria / Technique University of Berlin – Germany

• A Model Driven Engineering Based Method for Scheduling Analysis
  Yessine HADJ KACEM, Adel MAHFOUDHI, Walid KARAMTI, Mohamed ABID
  CES, National Engineering School of Sfax (ENIS) – Tunisia

• Failures analysis of systems modeled by Mixed Fault Trees
  Sahbi GHACHEM, Ayachi ERRACHDI, Kamel BENOTHMAN, Mohamed BENREJEB
  Unit of research LARA Automatic, National School Engineers of Tunis (ENIT) – Tunisia

• A SystemC QoS router design with virtual channels reservation in a wormhole-switched NoC
  Mohamed HORCHANI, Mohamed ATRI, Rached TOURKI
  EμE Laboratory, Faculty of Sciences Monastir – Tunisia

• An Ultra High Speed Low-Power CMOS Integrated Current Comparator
  Soheil ZIABAKHSH , Hosein Alavi RAD, Alireza SABERKARI , Shahriar Baradaran SHOKOUHI
  University of Guilan – Iran / Iran University of Science and Technology – Iran

• PID Control Implementation using FPGA Technology
  Abdesselem TRIMECHE, Anis SAKLY, Abdelatif MTIBAA, Mohamed BENREJEB
  LARA-ENIT – Tunisia / ENIM – Tunisia

• New speech processor and Ultrasonic Sensors Based Embedded system to Improve the Control of a Motorised Wheelchair
  Mohamed FEZARI, Abd-Erahman KHATI
  Faculty of Engineering, University of Annaba – Algeria

• Systematic design of CCI(II)(III)s by combining UGCs
  E. Tlelo-Cuautle, D.Moro-Frías, Mourad FAKHFAKH
  INAOE – Mexico / ENIS – Tunisia

• Wide Dynamic Range Current-to-Voltage Converters
  Chunyan WANG
  Department of Electrical and Computer Engineering, Concordia University – Canada

• Power-delay Efficient Technology Mapping of BDD-based Circuits Using DCVSPG Cells
  Gopal PAUL, Rohit REDDY, Jyotirmoy GHOSH, Ajit PAL, C. R. MANDAL, Bhargab B. Bhattacharya
  Indian Institute of Technology – India / ACM Unit, Indian Statistical Institute – India

• A Delay Efficient Robust Self-Timed Full Adder
  Padmanabhan BALASUBRAMANIAN, Doug EDWARDS
  The University of Manchester – United Kingdom

• Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion
  Laiq HASAN, Zaid AL-ARS, Zubair NAWAZ, Koen BERTELS
  Computer Engineering Laboratory, Delft University of Technology – The Netherlands

• Low Power Design of On-line Testers for Digital Circuits Using State Encoding
  Gopal PAUL, Santosh BISWAS, Ajit PAL, C. R. MANDAL
  IIT-Kharagpur – India / IIT-Guwahati – India

• A Novel Fault Tolerant Design and an Algorithm for Tolerating Faults in Digital Circuits
  R.V. KSHIRSAGAR, R.M.PATRIKAR
  Priyadarshini College of Engg. & Arch. – India / Visvesvaraya National Institute of Tech – India

• Pseudo-Linear Automatic Gain Control System Based on Nanoscale Field Effect Diode and SOI-MOSFET
  Farzan JAZAYERI, Samaneh SOLEIMANI-AMIRI, Behzad EBRAHIMI, Behjat FOROUZANDEH, Hamid-Reza AHMADI, Farshid RAISSI
  School of Electrical and Computer Engineering, University of Tehran – Iran / Department of Electrical Engineering, K. N. Toosi, University of Technology – Iran

IDT’08 Workshop > Sunday, 21^st of December

• DSP implementation and performances evaluation of 1D and 2D DWT using the lifting scheme
  Ihsen BEN HNIA-GAZZAH, Chokri SOUANI, Kamel BESBES
  LMI, Faculty of Sciences at Monastir – Tunisia

• An Efficient Hardware Architecture Design for H.264/AVC intra 4X4 Algorithm
  Hassen LOUKIL, Bilel KAANICH, Nouri MASMOUDI, Ahmed BEN ATITALAH, Patrice KADIONIK
  LEIT-ENIS – Tunisia / High Institute of Electronics and Communication, University of Sfax – Tunisia / IMS laboratory –ENSEIRB, University Bordeaux 1 – France

• Efficient FPGA Prototyping of Fixed Sphere Decoder for MIMO Systems
  Mohamed S. KHAIRY, Mohamed M. ABDALLAH, S. E.-D HABIB
  Electronics and Communications Department, Faculty of Engineering, Cairo University – Egypt

• Low-Power Flexible GF(p) Elliptic-Curve Cryptography Processor
  Hamid Reza AHMADI, Ali AFZALI-KUSHA
  School of Electrical and Computer Engineering, University of Tehran – Iran

• LAR method : from algorithm to synthesis for an embedded low complexity image coder
  Olivier DÉFORGES, Marie BABEL
  IETR/INSA Rennes – France

• External DDR2-Constrained NOC-Based 24-Processors MPSOC Design and Implementation on Single FPGA
  Zoukun WANG, Omar HAMMAMI
  ENSTA Paris Tech – France

• Corona: Ring-Based Interconnected Topology For On-Chip Network
  Maryam BAHMANI, Midia RESHADI, Ahmad KHADEMZADEH, Akram REZA
  Islamic Azad University, Science and Research Branch – Iran / Iran Telecommunication Research Center – Iran

• Multi-FPGA Emulation of a 48-Cores Multiprocessor with NOC
  Xinyu LI, OMAR HAMMAMI
  ENSTA Paris Tech – France

• Impact of Interconnection Networks in a Massively Parallel FPGA Architecture on a Parallel Reduction Algorithm
  Mouna BAKLOUTI, Philippe MARQUET, Mohamed ABID, Jean Luc DEKEYSER
  CES-ENIS – Tunisia /LIFL-INRIA – France

• An Extensible Framework For Fast Prototyping Of Multiprocessor Dataflow Applications
  Jonathan PIAT, Mickaël RAULET, Maxime PELCAT, Pengcheng MU, Olivier DÉFORGES
  IETR-INSA of RENNES – France

• Challenges and solutions in configuring, rapid developing and deploying of a QoS-enabled component middleware
  Mohamed MAZOUZI, Salem HASNAOUI, Mohamed ABID
  CES-ENIS – Tunisia / Communication Systems Research Laboratory, ENIT – Tunisia

• Efficient Tests and DFT for RAM Address Decoder Delay Faults
  Said HAMDIOUI, Zaid AL-ARS
  Faculty of EE, Mathematics and CS, Delft University of Technology – The Netherlands

• Evaluation of SRAM Faulty Behavior Under Bit Line Coupling
  Zaid AL-ARS, Said HAMDIOUI
  Faculty of EE, Mathematics and CS, Delft University of Technology – The Netherlands

Chair: Yervant Zorian – Virage Logic, USA

Title: Advances in Boolean Satisfiability and its Application in ED

Keynote speaker: Fadi ALOUL

University:  American University of Sharjah

Abstract: In this talk, an overview of the latest advances in SAT technology will be provided. Specifically, the input format of SAT solvers and the common SAT algorithms used to solve decision/optimization problems will be described. In addition, the speaker will highlight the use of SAT algorithms in solving a variety of EDA decision and optimization problems. This should guide researchers in solving their existing decision/optimization problems using the new SAT technology. Finally, a prospective on future work on SAT will be provided.

Moderator:

Panelists:

IDT’08 Workshop > Monday, 22^nd of December

Chair: Ashraf SALEM – Ain Chams University, Egypt

Title: From MARTE to SystemC/VHDL

Keynote speaker: Jean-Luc Dekeyser

University: LIFL-INRIA, University of Lille, France

Abstract: This keynote will present the Gaspard2 model driven engineering framework for the co-design of component-based intensive signal processing applications on multiprocessor systems-on-chip. This framework is implemented as an Eclipse-based application using the Eclipse Modeling Framework. The input language of this framework is a subset of the MARTE standard UML profile with a clearly defined semantics dedicated to multidimensional data-flow applications. The hardware platform is also modeled with MARTE as well as the allocation of the application to the hardware platform.  From the MARTE specification of the allocated application, Gaspard2 is able to automatically generate various codes for verification with synchronous reactive tools, simulation with SystemC or synthesis with VHDL.

• Generation of Test Programs for the Assertion-Based Verification of TLM Models
  Luca FERRO, Laurence PIERRE, Yves LEDRU, Lydie DU BOUSQUET
  TIMA, INPG/UJF/CNRS – France / LIG – France

• A Novel Approach for the Identification of Totally Symmetric Boolean Functions in the Application of Efficient System Design
  Gopal PAUL, Ashish TIWARI, Ajit PAL, C. R. Mandal
  Indian Institute of Technology – India

• Assertion-Based Verification and On-line Testing in Horus
  Yann ODDOS, Katell MORIN-ALLORY, Dominique BORRIONE
  TIMA, INPG/UJF/CNRS – France

• Mapping Timed Automata to B
  Anaheed AYOUB, Ayman WAHBA, Mohamed SHEIRAH
  Mentor Graphics – Egypt / Faculty of Engineering, Ain Shams University – Egypt

• Temporal Reduction in Time Petri Net
  Medesu SOGBOHOSSOU, David DELFIEU
  IRCCyN – France

• Disydent evaluation for the design of Multimedia systems
  Ahmed Chiheb AMMARI, Hajer HARBEGUE, Abderrazek JEMAI, Hajer KRICHENE ZRIDA
  MMA-INSAT – Tunisia / LIP2-ENIT – Tunisia / CES-ENIS – Tunisia

• An Embedded System for Real-Time Traffic Sign Recognizing
  Amin SOUKI, Lotfi BOUSSAID, Mohamed ABID
  CES-ENIS – Tunisia / ENIM – Tunisia / CES-ENIS – Tunisia

• A Novel Scheduling Algorithm for Dynamically Reconfigurable Computing Systems
  Bouraoui OUNI, Ramzi AYADI, Abdellatif MTIBAA, Mohamed ABID
  E.μ.M-FSM – Tunisia / CES-ENIS – Tunisia

• OLLAF : a Dual Plane Reconfigurable Architecturefor OS Support
  Samuel GARCIA, Bertrand GRANADO
  ENSEA-ETIS, University of Cergy Pontoise – France

• Left to Right Serial Multiplier for Large Numbers on FPGA
  H. BESSALAH, K. MESSAOUDI, M. ISSAD, N.ANANE, M.ANANE
  CDTA – Algeria / National informatics institute INI – Algeria

• Enslavement and Control in DQ Synchronous Frame for using a Cascade Multilevel NPC Structure
  F. BOUCHAFAA, S. AREZKI, M. BOUDOUR, E.M.BEKOUK
  LIES, University of Science and Technology – Algeria / LPC, Polytechnic National School Algiers – Algeria

• A Comparison Study between Static and Dynamic Recurrent Neural Networks Based Adaptive Control Of Nonlinear Multivariable Systems
  T. A. AL-ZOHAIRY
  Community collage in ALRiyadh, King Saud University – Kingdom of Saudi Arabia

• A composition-based approach for the development of Automated Embedded Systems
  Olfa MOSBAHI, Jacques JARAY, Samir BEN AHMED
  LORIA-INRIA Lorraine – France / MOSIC-ENIT – Tunisia

• Specification and Verification of Technical Plant Behavior with Symbolic Timing Diagrams
  Sebastian PREUßE, Hans-Michael HANISCH
  University Halle-Wittenberg, Germany

• Effect of a pulsed power supply on the ultra violet radiation and electrical characteristics of low pressure mercury discharge
  Mounir BEN MUSTAPHA, Brahim MRABET, Lotfi BOUSLIMI, Abdlejelil CHAMMAM, Mongi STAMBOULI
  ESSTT, Tunisia